Control Unit Design

For each cycle, the control signals depend only on the instruction opcode.
This table shows all the control signals.

The control unit is just a combinational logic circuit which can be implemented by discrete logic or by a PLA.

Worst Case Timing

The worst case timing is for a 'lw' instruction because this has the longest path through the datapath.

Drawbacks of Single Cycle Processor

PC's Clock -to-Q +
Instruction Memory Access Time +
Register File Access Time +
ALU Delay (address calculation) +
Data Memory Access Time +
Register File Setup Time +
Clock Skew

A Multiple Cycle Implementation

Advantages of the multiple cycle processor:

Choosing the cycles

Each cycle must complete a part of the instruction.
Worst case = load
Timing for load:

 Datapath for the multiple cycle processor

Control Unit Design