Datapath Design

Performance Example: The MIPS Instruction Formats An Abstract View of the Implementation
 

Clocking Methodology

The Critical Path

 Steps in the Design of a Processor

RTL: The ADD Instruction RTL: The Load Instruction

Combinational Logic Elements

Adder

MUX

ALU

 

Storage Element: Register

Storage Element: Register File


 

Storage Element: Idealised Memory


 

Overview of the Instruction Fetch Unit

Datapath for Register-Register Operations


 

Register-Register Timing

The OR Immediate Instruction

Datapath for Logical Operations with Immediate

R[rt] <- R[rs] op ZeroExt[imm16]] Example: ori rt, rs, imm16

The Load Instruction

Datapath for Load Operations


R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16

The Store Instruction

Datapath for Store Operations


Mem[R[rs] + SignExt[imm16] <- R[rt]] Example: sw rt, rs, imm16

The Branch Instruction

Datapath for Branch Operations


beq rs, rt, imm16 We need to compare Rs and Rt!

Next Address CalculATION

The PC could be a  32-bit byte address into the instruction memory but our instructions are fixed length so use a 30-bit PC.
Sequential operation: PC = PC + 1
Branch operation: PC = PC + 1 + SignExt[Imm16]
Instruction Memory Address = PC * 4

The Jump Instruction

Instruction Fetch Unit

Complete Single Cycle Datapath

Control signals are shown underlined