Buses: Connecting I/O to Processor and Memory

Sometimes shared bus with memory, sometimes a separate I/O bus




Synchronous and Asynchronous Bus

A Handshaking Protocol

Increasing the Bus Bandwidth

Bus Arbitration

Any device that can control the bus is called a bus master

The Daisy Chain Bus Arbitrations Scheme

Giving Commands to I/O Devices

Notifying the OS


Check the device a regular intervals.


Interrupt Driven Data Transfer

Delegating I/O Responsibility from the CPU: DMA



Block Diagram of a DMA Controller

Sequence of operations - Input:

  1. CPU loads registers - Address, Count and Device
  2. CPU Sets Status to Input
  3. Controller asks for bus
  4. Gets bus - does read from device, puts Address on the bus, does write to memory and decrements count.

  5. Repeat 4 until count=0
  6. Interrupt CPU to signal end of transfer
 Output is similar but status is set to Output and data is read from memory and written to the output device.