A Pipelined Processor

Key Ideas Behind Pipelining

Pipelining the Load Instruction

The Four Stages of R-type

Pipelining the R-type and Load Instruction

Problem:

Important

Solution 1: Insert "Bubble" into the Pipeline

Solution 2: Delay R-type's Write by One Cycle

The Four Stages of Store

The Four Stages of Beq

A Pipelined Datapath

The Instruction Fetch Stage

Instruction

lw $1, 0x100($2) $1 <- Mem[($2) + 0x100]

Fetch

The Instruction Unit

The Decode / Register Fetch Stage

Address Calculation Stage

The Execution Unit

Memory Access Stage

Write Back Stage

How About Control Signals?

Pipeline Control

Another Pipelining Example.

Pipelining Example: End of Cycle 4

Pipelining Example: End of Cycle 5

Pipelining Example: End of Cycle 6

Pipelining Example: End of Cycle 7

Delayed Branches

Delayed Loads

Summary

Single Cycle, Multiple Cycle, vs. Pipeline