So far we have assumed that all logic devices are infinitely fast.
Outputs immediately reflect inputs.
In practice this is not the case. There is a short delay between an input logic level changing and the corresponding output change.
Gate delays for TTL are typically 5 nanoseconds.
20 cm of wire will also delay a signal by 1 nanosecond.
A + = TRUE
However consider what happens when the signal A goes from 1 to 0
This spurious 0 is called a glitch.
These glitches may or may not have disastrous effects.
It is possible to design circuits that have no glitches. This requires extra hardware and considerable effort.
Another approach is to design circuits that are insensitive to glitches. Wait a fixed time after a change - during which the glitches will go away.
This idea is the basis for clocked circuits that we will come to later.
If we loop the output of a circuit back into its input, we have a condition called feedback, and some interesting results are obtained.
This circuit will oscillate rapidly
Will eventually settle on one input 0 and the other 1 (either way)
Consider what happens when S and R are both 0
If Q is 0:
the top NOR will have 0 0 as inputs and will output 1
the bottom NOR will have 1 0 as inputs and will output 0
=> the state is stable
if Q is 1:
the top NOR will have 0 1 as inputs and will output 0
the bottom NOR will have 0 0 as inputs and will output 1
=> the state is stable
If S is switched to a 1
the top NOR will have 1 X as inputs and will output 0
the bottom NOR will have 1 0 as inputs and will output 1
=> Q is forced to be a 1 (S stands for Set)
If R is switched to a 1
the bottom NOR will have 1 X as inputs and will output 0
=> Q is forced to be a 0 (R stands for Reset)
RS Flip-flops are useful for switch debouncing.
Switches make and break several times while in close contact.
Q will be Set to 1 if switch makes contact with S
Q will stay at 1 despite make/breaks on S until switch touches R
Circuits can use a clock to provide timing pulses. Logic levels can be read on the clock pulse, which is allowed to go high only when glitches are unlikely.
The RS Flip-flop can be clocked.
The output of the AND gates will only reflect S and R when the Clock is 1
When the Clock is 0 the outputs of the AND gates are always 0
The X output of a RS Flip-flop is normally
One problem with the RS Flip-flop is what happens when R and S are 1.
In this state the only stable state is both Q and 0 !
If both R and S return to 0 simultaneously Q jumps to 1 or 0 at random
otherwise Q will reflect which one returned to 0 last.
Clocked D Flip-flop
The D flip-flop removes this ambiguity
The Clock can now be considered a Strobe. A single clock pulse.
When the strobe is high, the value of D will be transferred to Q
Q will remain at that value until the strobe returns to a high state.
The D Flip-flop acts as a simple 1 bit memory.
As described, this type of flip-flop is level triggered. It depends on the strobe or clock being in a high state.
In practice this is not so desirable. It is better to transfer the value of D to the flip-flop when the strobe changes from a 0 to a 1
This is called edge triggered.
Edge triggered flip-flops are far more common.
They can be either 0 ->1 rising edge, or 1->0 falling edge
Clocked J-K Flip-flop
Rather than removing the ambiguity of the RS flip-flop as in the D flip-flop, the J-K flip-flop makes use of it.
J is equivalent to s. When J = 1 => Q becomes 1
K is equivalnet to R. When K = 1 => Q becomes 0
When J=K=1 => Q becomes
The J-K flip-flop toggles the output when J=K=1.
Given a regular clock and J=K=1 the Q output will be a clock with half the frequency.
We construct a register by connecting together a group of D flip-flops
All the flip-flops load simultaneously from the data in lines
A bus is a common set of wires connecting multiple devices together.
Buses are used to connect the data and address lines between computers, memory and i/o devices.
One problem with normal logic components is that their outputs are always active - either a 1 or a 0 (5V or Gnd).
If we connect the output of two gates together, where one output is a 0 and the other is a 1, then the result will be somewhere in between
If we want to use a bus architecture we must make sure that only one device at a time outputs a logic signal of 0 or 1
All other devices must go into a high impedance state
ie they look like they are not connected at all.
Tri-state devices have this capability.
A tri-state device is like a normal gate but with the added capability of going into this off-line mode.
In tri-state devices the OE output-enable line drives the outputs into this third state rather than into the 0 logic state as previously.
Not all devices are tri-state. To connect these devices to a bus we need to put a tri-state driver chip in between the device and the bus.
A tri-state driver just sends its input to its output, but also has an OE input to allow the output to go ‘not connected’.
159.233 Lecture 4 -