Power Control

The PCON register determines the idle modes of the 2051.

putting a 1 in either of the 2 low order bits will cause the 2051 to go into idle or power-down mode.

Idle mode (01h) will allow interrupts, keep the timers going and preserve RAM.

An interrupt or reset will revert to normal operation

Power-down mode will preserve RAM but needs a reset to resume.

(resets will alter the contents of SFR).

Power-down uses considerable less power than idle mode, which again uses less power than normal operations.


Interrupts can be generated by the timers, the serial port or by an external event connected via a parallel input.

The action taken by the processor is:

The LCALL branches to specific locations in memory:

0003h Ext Int 0

000bh Timer 0 interrupt

0013h Ext Int 1

001bh Timer 1 interrupt

0023h Serial Port

Either the service routine can fit in 8 bytes (possible) or it will JMP to a longer routine.

Interrupts can be controlled by using the IE register

EA - - ES ET1 EX1 ET0 EX0

EA is a global interrupt enable bit. Interrupts will not happen unless this is set.

ET1/0 are the timer interrupts

ES is the serial interrupt.

The serial interrupt can happen either on RI or TI being set. The ISR will have to read these bits to decide which requires servicing. These bits should be cleared by software.

It is good programming practice to put an reti instruction at each of the LCALL locations even if no interrupts are expected! If one does happen the program will jump into 'no-where'.

Interrupts can be given a priority level.

Those of higher priority can interrupt a running lower priority ISR.

The 2051 has only a two level priority scheme. Each interrupt can be assigned 0 (low priority) or 1 (high priority).

Interrupts at the same priority level cannot interrupt each other.

Levels are set in the IP register:

- - - PS PT1 PX1 PT0 PX0

Which interrupt happens is indicated by the location involved in the LCALL

159.233 Assembler 10 - 2