The MIPs Datapath

Unlike the Pico-computer the MIPs computer has several Buses connecting it’s components together.

We’ll see later that this enables us to ‘Pipe-line’ instructions.

The processor is built from several sub-sections.

The first section is the Program counter and the Instruction memory.

In this version of the MIPs processor, we keep instruction memory and data memory separate.

The Program Counter is used as the address line to the instruction memory.

As each instruction is 32bits wide, each time we retrieve an instruction we have to add 4 to PC to point to the next instruction. This will be modified later to cope with jumps.

R-type instructions:

These instructions only involve Registers and the ALU - remember that the MIPS chip has a load/store architecture. Data stored in memory must first of all be transferred to a register before performing any operation on it.

The instruction produces the numbers of each of the three registers involved:

add $4,$10,$14

will add register 14 to register 10 and put the result into register 4

The 32 bits making up this instruction has the form

Opcode Rs Rt Rd Shamt Subfct

each of the register fields are 5 bits.

The register file allows 3 registers to be selected.

The two read registers, Rs and Rt are selected by the instruction and the data stored in them appears as read data1 and read data2

The write register Rd gets its data from the output of the ALU.

The ALU is controlled by a combination of Opcode/Shamt/Subfct

I-type instructions

These instructions load/store data from memory to register

lw $1,100($2)

loads into register 1, the data stored at 100 + contents of register 2

We need to be able to add the offset stored in the instruction to a register.

The offset is only 16 bits, so has to be extended to 32 bits for the ALU.

If the offset is negative we need to preserve the sign bit (ASR).

Branch instructions

These also have a 16bit immediate data in the instruction, which needs to be added to the program count if the branch is taken

As the PC is always a multiple of 4, the immediate value has also to be shifted left by 4.

The ALU produces an output that will control whether the conditional branch is taken or not.

The branch address is formed from (PC + 4) + the displacement

These separate parts can now be combined into one complete picture for the MIPs processor architecture.

The multiplexors have been included so that we can control which data is to be forwarded.

The MUX sending data to the PC will be controlled by the branch control logic

The MUX before the adder will be controlled by whether the instruction is a load/store or not.

The MUX after the Data mem will control whether either the output from the ALU is written back to the register bank (an R-type instruction), or whether data from memory is written to a register (a load instruction)

159.233 Hardware 17 - 1