Instruction set design


The Pico-computer has 7 instructions, LDA IN ADD etc, they are of variable size – the IN instruction is just a single byte, but LDA takes 2 bytes. They also take a variable number of clock cycles IN takes 2 less cycles than LDA. They are also the idea of one person – others might have different ideas of what constitutes a good instruction set.


The controller specifies how the instructions are implemented by the hardware and in general they follow 5 basic steps:


Fetch: an instruction is brought into the control unit from memory.


Decode: The control unit decodes the instruction to determine the sequence of events necessary to execute it.


Memory: Any data necessary for the instruction are fetched from memory


Execute: The operation is performed


Write: Results of the operation may be written to memory


Each machine code, expressed in Assembler language contains:


OpCode the operation to be performed and

Operands the rest of the instruction

Addresses some of the operands may be addresses of data


Eg

ADD AX,[102]


The OpCode is ADD, there are two operands AX and [102], and one address [102]


Assembler language syntax is specific to the processor, and varies widely.

Types of instructions


Five address machines

Machines with only one instruction type:


If we need to put all the information necessary into a single instruction, then it must contain the following:


OpCode Dest Addr, Src1 Addr, Src2 Addr, Cond Code, True Addr,

False Addr


5 addresses -> 5 address machine

e.g.


SUB [0],[1],[2],NZ,4,5


Which subtracts the value stored at location 2 from that at 1 and stores the result in 0. If the result is not zero, then the next instruction is at location 4 otherwise the next instruction is at 5.


Some very early computers used this format, but it is not used today. It has the disadvantage that all instructions are very big. Addresses are normally 32 bits long, so the instruction will be ~160 bits long.


We can make the instructions shorter if we allow ourselves two types of instructions and 2 further registers:

Three address machines

Machines with two instruction types.


Implement a Program Counter. If we order our program sequentially, then the False Addr can be set to default to the next instruction (PC + 1).


Implement a Flags Register. Condition Codes set by one instruction are remembered and can be tested by another.


The two instruction types are:


OpCode Dest Addr, Src1 Addr, Src2 Addr :Arithmetic/Logic instrs


OpCode Cond Code, True Addr :Control instructions



The longest instruction now has 3 addresses

e.g.


SUB [0],[1],[2]

JNZ 4


Two address machines

Three address machines still have a long instruction length (3 * 32 = 96), we can cut out the Dest Addr by assuming it is the same as one of the Src Addr.


This is often the case, but if it isn’t we need to invent an extra operation MOV.


We still have two types of instructions:

OpCode Dest/Src1 Addr, Src2 Addr :Arithmetic/Logic instrs

:Memory/Memory move


OpCode Cond Code, True Addr :Control instructions


The longest instruction now has 2 addresses -> 2 address machine

e.g.


MOV [0],[1]

SUB [0],[2]

JNZ 4


Although this particular program is still the same length as the other two, in general programs will be shorter as several ALU instructions performed in sequence will only be ~64 bits. Shorter programs tend to be slower, but this is not always the case.

One address machines

Two address machines can be made even shorter, by implementing special temporary locations within the processor – Registers.


If there is only one register, its called the Accumulator. Several registers are called either by their special function or by a more general R1, R2 etc. There will only be a few registers ~32 so they can be encoded using only a few bits, rather than the 32 needed for memory.


We now have four types of instructions:

OpCode Dest/Src1 Addr, Src2 Reg :Memory/Register moves


OpCode Cond Code, True Addr :Control instructions


OpCode Dest/Src1 Reg, Src2 Addr :Register/Memory moves


OpCode Dest/Src1 Reg, Src2 Addr :Register/Memory ALU


The longest instruction now has 1 address -> 1 address machine

e.g.


MOV A,[1]

SUB A,[2]

MOV [0],A

JNZ 4

Zero address machines

We can’t have instructions that do not access memory – but we can restrict the ALU operations to be Register/Register.


We now have four types of instructions:


OpCode Dest/Src1 Addr, Src2 Reg :Memory/Register moves


OpCode Cond Code, True Addr :Control instructions


OpCode Dest/Src1 Reg, Src2 Addr :Register/Memory moves


OpCode Dest/Src1 Reg, Src2 Reg :Register/Register ALU


e.g.


MOV A,[1]

MOV B,[2]

SUB A,B

MOV [0],A

JNZ 4


Often these machines are referred to as Load/Store. Only Registers are involved with the ALU. Some processors allow 3 registers to be specified for ALU operations, the MIPs processor that we will be looking at is one of them.

Stack machine:


One, final, zero address instruction set is for a stack based machine


OpCode Cond Code, True Addr :Control instructions


PUSH Src Addr :Stack operation


POP Src Addr :Stack operation


e.g.


PUSH [1]

PUSH [2]

SUB

POP [0]

JNZ 4


There are a few stack machines around today – e.g. the Inmos Transputer.


159.233 - Lecture 15 - 1